One or more embodiments of the present invention generally relate to a clock generating method and a clock generating circuit for generating a clock to be supplied to a control circuit and a functional module in a semiconductor chip on which the functional module and the control circuit controlling the operation of the functional module by communication with the functional module are mounted.
With the progress of segmentalization in the manufacturing process of semiconductor integrated circuits, the semiconductor chips increase in size and are multi-functionalized. For example, in a design technique for semiconductor integrated circuit called system-on-chip (SOC), in addition to one or more functional modules each performing a predetermined function, a control circuit, such as a central processing unit (CPU), which controls the operations of the functional modules by communicating therewith, may be mounted on a semiconductor chip. Further, suppression of stand-by power consumption of a circuit has been carried out by means of lowering the frequency of an operation clock when the circuit does not operate.
When a semiconductor chip increases in size, a physical wiring distance of an operation clock connected to the functional modules from a clock generating circuit may increase up to several millimeters. Accordingly, even when the control circuit and the functional modules are connected to the same operation clock, the functional modules are supplied with operation clocks that are delayed depending on the wiring distance and of which the phases deviate from the phase of the operation clock supplied to the control circuit. Thus, the control circuit and the functional modules may not correctly communicate with each other.
JP 2005-38159 A (Patent document 1) describes that a master clock signal is divided and output as a first divided clock signal, a clock skew of a second divided clock signal is reduced by synchronizing the first divided clock signal with the master clock signal to output the second divided clock signal, and the second divided clock signal having the same phase as the first divided clock signal is supplied to plural logic circuits in a semiconductor chip.
JP 2007-189293 A (Patent document 2) describes that a first clock signal is divided to generate a second clock signal, and a third clock signal having the period of the second clock signal and having the same timing of change in logic level as that of the first clock signal is generated from the first and second clock signals, whereby a skew due to on-chip variation of transmission lines of the first clock signal and the third clock signal is suppressed and timing closure is improved.
In Patent documents 1 and 2, the divided clocks are held again in synchronization with the source clock to generate a regenerated clock and distributing the regenerated clock to the functional modules so as to suppress an influence of OCV (on-chip variation: characteristic variation in the same semiconductor chip). However, in Patent documents 1 and 2, when the division ratio of the divided clocks is variable, the phases of the divided clocks supplied to the control circuit and the functional modules deviate from each other due to flip-flops (FF) for generating the regenerated clocks, of which the number of stages is fixed. Thus, the control circuit and the functional modules cannot correctly communicate with each other.
FIG. 7 is a circuit diagram illustrating an example of a configuration of a conventional clock generating circuit. In a semiconductor chip on which functional modules (A and B) 14 and 16 and a control circuit 12 controlling the operations of the functional modules 14 and 16 by communicating therewith are mounted, a clock generating circuit 56 illustrated in the drawing generates delayed clocks to be supplied to the control circuit 12 and the functional modules 14 and 16, and includes a frequency division circuit 58 and clock synchronization circuits 60 and 62.
The frequency division circuit 58 divides a source clock by m (where m is an integer equal to or greater than 2) to generate a divided clock having a 1/m frequency of the frequency of the source clock.
The clock synchronization circuit 60 generates delayed clock A by delaying the divided clock by four clocks in synchronization with the source clock and supplies generated delayed clock A to the functional module 14 operating in synchronization with delayed clock A.
The clock synchronization circuit 62 generates delayed clock B by delaying the divided clock by two clocks in synchronization with the source clock and supplies generated delayed clock B to the functional module 16 operating in synchronization with delayed clock B.
When the clock synchronization circuits 60 and 62 are not provided, the functional modules 14 and 16 are supplied with variable divided clocks, which are delayed depending on the wiring distances.
The number of clocks, such as four clocks and two clocks, by which the divided clock is delayed by the clock synchronization circuits 60 and 62 is the number of clocks by which it is necessary to delay the variable divided clocks in synchronization with the source clock, and is calculated for each of the variable divided clocks connected to the functional modules 14 and 16 depending on the wiring distance of each of the divided clocks connected to the functional modules 14 and 16 from the frequency division circuit 58 when the clock synchronization circuits 60 and 62 are not provided, in order to operate the control circuit 12 and the functional modules 14 and 16 in synchronization with the divided clocks.
The clock synchronization circuit 60 includes FFs (delay circuits) 64, 66, 68, and 70 respectively at four stages connected in series, in accordance with four clocks to be delayed. The source clock is input to clock input terminals of the FFs 64, 66, 68, and 70, and the divided clock is input to a data input terminal of the FF 64 at the first stage. Regenerated clocks 1 to 3 and delayed clock A are output from data output terminals of the FFs 64, 66, 68, and 70, respectively.
The divided clock is delayed by one clock by each of FFs 64, 66, 68, and 70 at four stages in synchronization with the rising of the source clock. As a result, delayed clock A, which is delayed by four clocks of the source clock from the divided clock, is output from the clock synchronization circuit 60.
Similarly, the clock synchronization circuit 62 includes FFs 72 and 74 respectively at two stages connected in series in accordance with two clocks to be delayed. The source clock is input to clock input terminals of the FFs 72 and 74, and the divided clock is input to a data input terminal of the FF 72 at the first stage. Regenerated clock 1 and delayed clock B are output from data output terminals of the FFs 72 and 74, respectively.
The divided clock is delayed by one clock by each of the FFs 72 and 74 at two stages in synchronization with the rising of the source clock. As a result, delayed clock B, which is delayed by two clocks of the source clock from the divided clock, is output from the clock synchronization circuit 62.
In the clock generating circuit 56, the source clock is in-divided by the frequency division circuit 58, and, thus, a divided clock is generated.
Subsequently, delayed clock A, which is delayed by four clocks from the divided clock, is generated in synchronization with the rising of the source clock by the clock synchronization circuit 60. Delayed clock A is supplied to the functional module 14. Delayed clock B, which is delayed by two clocks from the divided clock, is generated in synchronization with the rising of the source clock by the clock synchronization circuit 62. Delayed clock B is supplied to the functional module 16.
FIG. 8 is a timing diagram illustrating an example of an operation of the clock generating circuit illustrated in FIG. 7 when the divided clock is a two-divided clock.
When the divided clock is a two-divided clock, the divided clock is alternately changed between a high level and a low level in synchronization with the rising of the source clock as illustrated in the timing diagram. Regenerated clocks 1 to 3 are changed in level in synchronization with the rising of the source clock as well and are delayed by one to three clocks of the source clock from the divided clock, respectively. Delayed clocks A and B are changed in level in synchronization with the rising of the source clock and are delayed by four clocks and two clocks of the source clock from the divided clock, respectively.
Accordingly, because delayed clocks A and B and the divided clock are synchronized and matched in phase, the control circuit 12 can correctly communicate with the functional modules 14 and 16 to control the operations thereof.
FIG. 9 is a timing diagram illustrating an example of an operation example of the clock generating circuit illustrated in FIG. 7 when the divided clock is a five-divided clock.
When the divided clock is a five-divided clock, the divided clock is alternately changed between a high level and a low level in synchronization with the rising of the source clock, as illustrated in the timing diagram. The high level of the divided clock is set to have a pulse width of two clocks of the source clock and the low level is set to have a pulse width of three clocks of the source clock. Regenerated clocks 1 to 3 are changed in level in synchronization with the rising of the source clock as well and are delayed by one to three clocks of the source clock from the divided clock, respectively. Delayed clocks A and B are changed in level in synchronization with the rising of the source clock and are delayed by four clocks and two clocks of the source clock from the divided clock, respectively.
Accordingly, because delayed clocks A and B and the divided clock are synchronized but deviate from each other in phase, the control circuit 12 cannot correctly communicate with the functional modules 14 and 16.
The configuration of the clock synchronization circuits 60 and 62 of the clock generating circuit 56 is provided for a case in which the divided clock is fixed to the two-divided clock. Accordingly, in the configuration of the clock generating circuit 56, when the divided clock is changed from the two-divided clock to a divided clock of a different division ratio, delayed clocks A and B and the divided clock deviate from each other in phase. Accordingly, the control circuit 12 cannot correctly communicate with the functional modules 14 and 16 and cannot control the operations thereof.